CSDFa:一个利用数据和管道并行性之间权衡的模型

Peter Koek, Stefan J. Geuns, J. Hausmans, H. Corporaal, M. Bekooij
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引用次数: 3

摘要

实时流处理应用程序,如软件定义无线电应用程序,通常在多处理器系统上并发执行。提出了一种统一的数据流模型和分析方法,可用于同时确定满足此类应用的时间约束所需的管道和粗粒度数据并行性的数量。然而,这个统一模型仅为同步数据流(SDF)图定义。不可能为更具表现力的模型(如循环静态数据流(CSDF))定义统一的模型,因为自动并发可能导致令牌和依赖项的顺序依赖于时间。本文介绍了具有自动并发性的循环静态数据流(CSDFa)模型。在CSDFa中,令牌有索引,令牌的消费顺序是静态的、与时间无关的。这允许在单个统一模型中表达和权衡管道和粗粒度数据并行性。此外,我们引入了一种新的循环缓冲区,它实现了与CSDFa模型使用的相同的静态顺序。此缓冲区上的操作开销与自动并发性的数量无关,自动并发性对应于CSDFa模型中的恒定触发持续时间。利用CSDFa模型在数据和管道并行性之间的权衡,以FMCW雷达处理管道的一部分为例进行了演示。我们表明,CSDFa模型可以优化处理单元和内存之间的平衡,从而显着减少硅面积。此外,减少允许的最大延迟可以将数据并行性所需的最小数量增加16倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
CSDFa: A Model for Exploiting the Trade-Off between Data and Pipeline Parallelism
Real-time stream processing applications, such as Software Defined Radio applications, are often executed concurrently on multiprocessor systems. A unified data flow model and analysis method have been proposed that can be used to simultaneously determine the amount of pipeline and coarse-grained data parallelism required to meet the temporal constraints of such applications. However, this unified model is only defined for Synchronous Data Flow (SDF) graphs. Defining a unified model for a more expressive model such as Cyclo-Static Data Flow (CSDF) is not possible, because auto-concurrency can cause a time-dependent order of tokens and dependencies. This paper introduces the Cyclo-Static Data Flow with Auto-concurrency (CSDFa) model. In CSDFa, tokens have indices and the consumption order of tokens is static and time-independent. This allows expressing and trading off pipeline and coarse-grained data parallelism in a single, unified model. Furthermore, we introduce a new type of circular buffer that implements the same static order as is used by the CSDFa model. The overhead of operations on this buffer is independent of the amount of auto-concurrency, which corresponds to the constant firing durations in the CSDFa model. Exploiting the trade-off between data and pipeline parallelism with the CSDFa model is demonstrated with a part of a FMCW radar processing pipeline. We show that the CSDFa model enables optimizing the balance between processing units and memory, resulting in a significant reduction of silicon area. Additionally, it is shown that reducing the maximum allowed latency increases the minimum required amount of data parallelism by up to a factor of 16.
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