一种自下而上的延迟故障表征方法

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI:10.1109/DFTVS.1991.199961

J. Zubairi, G.L. Craig

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引用次数: 4

摘要

将电感故障分析扩展到考虑影响电路时序性能的CMOS VLSI电路中的局部点缺陷。提出了一种确定性地在组合逻辑电路布局中引入点缺陷的方法。开发了一种方法和工具来描述由于缺失和额外的斑点缺陷而导致的延迟缺陷，并生成真实的延迟缺陷分布。

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A bottom-up methodology to characterize delay faults

Inductive Fault Analysis is extended to consider localized spot defects in CMOS VLSI circuits which impact circuit timing performance. A scheme of deterministic introduction of spot defects into layouts of combinational logic circuits is described. A methodology and tool is developed to characterize delay defects resulting from missing and extra spot defects and to generate realistic delay defect distribution.<>

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[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems

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