粒子阵列- Petri网硬件实现

[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools Pub Date : 1988-04-11 DOI:10.1109/CMPEUR.1988.4931

R. Hartenstein, A. Hirschbiel, M. Weber

{"title":"粒子阵列- Petri网硬件实现","authors":"R. Hartenstein, A. Hirschbiel, M. Weber","doi":"10.1109/CMPEUR.1988.4931","DOIUrl":null,"url":null,"abstract":"The authors describe a parallel hardware implementation of Petri nets using the Kolte array scheme. The main feature of the work is a way of solving accessing conflicts which can arise from parallelism within such arrays. A description is also given of an NMOS circuit technique, a Patil array generator, and a flexible field-reprogrammable Patil array circuit technique.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Patil array-a Petri net hardware implementation\",\"authors\":\"R. Hartenstein, A. Hirschbiel, M. Weber\",\"doi\":\"10.1109/CMPEUR.1988.4931\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe a parallel hardware implementation of Petri nets using the Kolte array scheme. The main feature of the work is a way of solving accessing conflicts which can arise from parallelism within such arrays. A description is also given of an NMOS circuit technique, a Patil array generator, and a flexible field-reprogrammable Patil array circuit technique.<<ETX>>\",\"PeriodicalId\":415032,\"journal\":{\"name\":\"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-04-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CMPEUR.1988.4931\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPEUR.1988.4931","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

作者描述了使用Kolte阵列方案的Petri网的并行硬件实现。这项工作的主要特点是一种解决访问冲突的方法，这种冲突可能由此类数组中的并行性引起。本文还介绍了一种NMOS电路技术、一种Patil阵列发生器和一种灵活的现场可编程Patil阵列电路技术

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Patil array-a Petri net hardware implementation

The authors describe a parallel hardware implementation of Petri nets using the Kolte array scheme. The main feature of the work is a way of solving accessing conflicts which can arise from parallelism within such arrays. A description is also given of an NMOS circuit technique, a Patil array generator, and a flexible field-reprogrammable Patil array circuit technique.<>

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[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools

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