Intel 10nm制程标准单元库的设计-技术协同优化

2018 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2018-12-01 DOI:10.1109/IEDM.2018.8614662

Xinning Wang, Ranjith Kumar, S. Prakash, Peng Zheng, Tai-Hsuan Wu, Q. Shi, Marni Nabors, Srinivasa Chaitanya Gadigatla, S. Realov, Chin-Hsuan Chen, Ying Zhang, K. Mistry, A. Yeoh, I. Post, C. Auth, A. Madhavan

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引用次数: 9

摘要

本文重点介绍了英特尔10nm节点上工艺技术、std. cell库产品和块级TFM的协同优化，为从高性能客户端/服务器到低功耗移动/物联网领域的产品提供了前所未有的扩展机会。10nm短高度库使晶体管密度从14nm扩展到2.7倍。更高的高度库进行了优化，以满足英特尔领先的客户端/服务器产品的性能和可靠性要求。在行业标准核心IP设计上，在std单元级别和块级别上分析PPA权衡。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design-Technology Co-Optimization of Standard Cell Libraries on Intel 10nm Process

This paper highlights the co-optimization of process technology, std. cell library offerings and block-level TFM on Intel 10nm node to enable unprecedented scaling opportunity for products ranging from high performance client/server to low power mobile/IoT segments. The 10nm short height library enables 2.7x transistor density scaling going from 14nm counterpart. The taller height libraries are optimized to meet performance and reliability requirements of Intel's leading edge client/server products. PPA trade-offs are analyzed both at std. cell level and block level on an industry standard Core IP design.

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2018 IEEE International Electron Devices Meeting (IEDM)

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