{"title":"Intel®版本的STAC-A2基准测试:以更少的努力获得更好的性能","authors":"Andrey Nikolaev, Ilya Burylov, S. Salahuddin","doi":"10.1145/2535557.2535566","DOIUrl":null,"url":null,"abstract":"Market risk analysis is a computationally intensive problem which requires powerful computing resources. To enable consistent comparisons of vendors' technologies in this area the Securities Technology Analysis Center (STAC*), with inputs from leading trading companies, universities, and high performance computing vendors, has created STAC-A2* specifications which describe realistic market risk analysis workloads.\n In this paper we analyze and compare the performance of STAC-A2 workloads on two systems based on Intel® processors: Intel® Xeon® processor E5 family and Intel® Xeon Phi#8482; coprocessor. We show the importance of algorithmic optimizations and a few mathematical building blocks such as random number generation, mathematical functions and matrix multiplications on overall performance of the benchmark. We demonstrate that changes made in response to this analysis provide an additional ~1.6x performance improvement of the STAC-A2 benchmark on the Intel Xeon processor E5 family and up to ~15x performance improvement on Intel Xeon Phi coprocessor-based systems compared with the previous version of the benchmark. Intel Xeon Phi coprocessor architecture is ~1.10--1.38x faster than 16-core Intel Xeon processor E5 family-based systems, depending on the problem size, while the 32-core Intel Xeon processor E5 is the fastest among all analyzed platforms.","PeriodicalId":241950,"journal":{"name":"High Performance Computational Finance","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Intel® version of STAC-A2 benchmark: toward better performance with less effort\",\"authors\":\"Andrey Nikolaev, Ilya Burylov, S. Salahuddin\",\"doi\":\"10.1145/2535557.2535566\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Market risk analysis is a computationally intensive problem which requires powerful computing resources. To enable consistent comparisons of vendors' technologies in this area the Securities Technology Analysis Center (STAC*), with inputs from leading trading companies, universities, and high performance computing vendors, has created STAC-A2* specifications which describe realistic market risk analysis workloads.\\n In this paper we analyze and compare the performance of STAC-A2 workloads on two systems based on Intel® processors: Intel® Xeon® processor E5 family and Intel® Xeon Phi#8482; coprocessor. We show the importance of algorithmic optimizations and a few mathematical building blocks such as random number generation, mathematical functions and matrix multiplications on overall performance of the benchmark. We demonstrate that changes made in response to this analysis provide an additional ~1.6x performance improvement of the STAC-A2 benchmark on the Intel Xeon processor E5 family and up to ~15x performance improvement on Intel Xeon Phi coprocessor-based systems compared with the previous version of the benchmark. Intel Xeon Phi coprocessor architecture is ~1.10--1.38x faster than 16-core Intel Xeon processor E5 family-based systems, depending on the problem size, while the 32-core Intel Xeon processor E5 is the fastest among all analyzed platforms.\",\"PeriodicalId\":241950,\"journal\":{\"name\":\"High Performance Computational Finance\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"High Performance Computational Finance\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/2535557.2535566\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"High Performance Computational Finance","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2535557.2535566","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Intel® version of STAC-A2 benchmark: toward better performance with less effort
Market risk analysis is a computationally intensive problem which requires powerful computing resources. To enable consistent comparisons of vendors' technologies in this area the Securities Technology Analysis Center (STAC*), with inputs from leading trading companies, universities, and high performance computing vendors, has created STAC-A2* specifications which describe realistic market risk analysis workloads.
In this paper we analyze and compare the performance of STAC-A2 workloads on two systems based on Intel® processors: Intel® Xeon® processor E5 family and Intel® Xeon Phi#8482; coprocessor. We show the importance of algorithmic optimizations and a few mathematical building blocks such as random number generation, mathematical functions and matrix multiplications on overall performance of the benchmark. We demonstrate that changes made in response to this analysis provide an additional ~1.6x performance improvement of the STAC-A2 benchmark on the Intel Xeon processor E5 family and up to ~15x performance improvement on Intel Xeon Phi coprocessor-based systems compared with the previous version of the benchmark. Intel Xeon Phi coprocessor architecture is ~1.10--1.38x faster than 16-core Intel Xeon processor E5 family-based systems, depending on the problem size, while the 32-core Intel Xeon processor E5 is the fastest among all analyzed platforms.