D. Chang, D. Lyon, Charles Chen, Leon Peng, M. Massoumi, M. Hakimi, Satish Iyengar, Ellen Li, Roque Remedios
{"title":"HaL内存管理单元的微架构","authors":"D. Chang, D. Lyon, Charles Chen, Leon Peng, M. Massoumi, M. Hakimi, Satish Iyengar, Ellen Li, Roque Remedios","doi":"10.1109/CMPCON.1995.512396","DOIUrl":null,"url":null,"abstract":"This paper discusses the architecture and implementation of HaL's 64-bit memory management unit (MMU). The MMU is responsible for virtual-to-physical address translations, data movement controls, bus interfaces among CPU/caches, memory subsystems; and I/O systems; and maintaining memory coherency among caches and memories.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"119 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Microarchitecture of HaL's memory management unit\",\"authors\":\"D. Chang, D. Lyon, Charles Chen, Leon Peng, M. Massoumi, M. Hakimi, Satish Iyengar, Ellen Li, Roque Remedios\",\"doi\":\"10.1109/CMPCON.1995.512396\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses the architecture and implementation of HaL's 64-bit memory management unit (MMU). The MMU is responsible for virtual-to-physical address translations, data movement controls, bus interfaces among CPU/caches, memory subsystems; and I/O systems; and maintaining memory coherency among caches and memories.\",\"PeriodicalId\":415918,\"journal\":{\"name\":\"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway\",\"volume\":\"119 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-03-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CMPCON.1995.512396\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPCON.1995.512396","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper discusses the architecture and implementation of HaL's 64-bit memory management unit (MMU). The MMU is responsible for virtual-to-physical address translations, data movement controls, bus interfaces among CPU/caches, memory subsystems; and I/O systems; and maintaining memory coherency among caches and memories.
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