Performance Effect of I/O Peripheral Dynamic Reconfiguration on FPGA

Embedded devices are equipped with specialized microcontrollers for each device. If an ultra-general purpose microcontroller with all peripherals existing, any kind of embedded device can be developed by such microcontroller. However, such microcontrollers cannot be built due to the scale and price. A dynamic partial reconfigurable microcontroller (DPR microcontroller), which has a function to switch circuits for each application, can realize an ultra-general purpose microcontroller that can be used for any application. For the realization and practical use of DPR microcontrollers, it is necessary to develop a hardware library-like structure in which optimized interface circuits for each peripheral device are designed in advance. In addition, the impact of dynamic switching of peripheral device interface circuits on performance has not been studied, so it is necessary to evaluate these effects. Using dynamic partial reconfiguration, we measure the execution time, circuit size of the entire system, and power performance improvement ratio of a single system that displays a binarized image on an LCD module after gray scaling and binarizing the image. The results show that the dynamic partial reconfiguration can be used to improve the performance of the system. As a result, we confirmed that the system works correctly even when dynamic partial reconfiguration is used. In addition, we were able to improve the processing speed by about 2.13 times compared with software processing, and reduce the circuit size by about 24%. We also achieved a 13.8-fold improvement in power consumption.