T. Furuyama, N. Kushiyama, Y. Watanabe, T. Ohsawa, K. Muraoka, Y. Nagahama
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A high random-access-data-rate 4 Mb DRAM with pipeline operation
A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e. a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAD access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family
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