容错多处理器工作站的体系结构

J. Banâtre, M. Banâtre, Gilles Muller
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引用次数: 6

摘要

提出了一种基于标准处理器与稳定存储板相关联的容错多处理器体系结构。简要介绍了稳定存储板的硬件结构和软件接口。详细介绍了容错多处理器的硬件结构,并分析了安全内核的一些功能。>表示项目的当前状态
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Architecture of fault-tolerant multiprocessor workstations
A fault-tolerant multiprocessor architecture that is based on standard processors associated with stable storage boards is presented. The hardware architecture of the stable storage board and its software interface are briefly described. The hardware organization of the fault-tolerant multiprocessor is detailed, and some functionalities of a secure kernel are examined. The current status of the project is indicated.<>
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