伪穷举测试中实现最大测试并发性的分区方法

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208129

R. Srinivasan, C. Njinda, M. Breuer

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引用次数: 3

摘要

组合电路的伪穷举测试通常需要多个测试会话和/或超过最小测试信号数量，即唯一输入序列。本文提出了一种划分组合电路的方法，使它们能够在单个测试会话中使用最少数量的测试信号进行伪穷举测试。在测试模式下，电路被逻辑划分，不相关的输入被组合以达到最大的测试并发性。

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A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing

Pseudo-exhaustive testing of combinational circuits usually requires multiple test sessions and/or more than a minimum number of test signals, i.e. unique input sequences. This paper presents a methodology for partitioning combinational circuits such that they can be pseudo-exhaustively tested with a minimal number of test signals in a single test session. Circuits are logically partitioned during test mode and unrelated inputs are combined to achieve maximal test concurrency.<>

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来源期刊

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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