14.9 Sub-sampling all-digital fractional-N frequency synthesizer with −111dBc/Hz in-band phase noise and an FOM of −242dB

The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLL's high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.