一个600兆赫DSP与24 Mb嵌入式DRAM与一个增强的指令集无线通信

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332772

Y. Adelman, D. Agur, T. Ben-Nun, O. Chalak, Z. Greenfield, R. Holzer, M. Jalfon, A. Kadry, E. Kraus, F. Lange, H. Meirov, A. Olofsson, O. Raikhman, D. Treves, S. Zur, R. Talmudi

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引用次数: 5

摘要

提出了一种具有24mb嵌入式DRAM、154个GOPS、4800个MMACS和40gb /s I/O吞吐量的600mhz通用DSP。该芯片包含超过60M晶体管，采用0.13 /spl mu/m 8M CMOS技术实现。

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A 600 MHz DSP with 24 Mb embedded DRAM with an enhanced instruction set for wireless communication

A 600 MHz general-purpose DSP with 24 Mb of embedded DRAM, 154 GOPS, 4800 MMACS, and 40 Gb/s I/O throughput is presented. The chip contains over 60M transistors and is implemented in 0.13 /spl mu/m 8M CMOS technology.

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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