Lixue Kuang, B. Chi, Lei Chen, Meng Wei, Xiaobao Yu, Zhihua Wang
{"title":"集成60GHz 5Gb/s QPSK发射机,片上T/R开关和65nm CMOS全差分锁相环频率合成器","authors":"Lixue Kuang, B. Chi, Lei Chen, Meng Wei, Xiaobao Yu, Zhihua Wang","doi":"10.1109/ASSCC.2013.6691070","DOIUrl":null,"url":null,"abstract":"An integrated 60GHz 5Gb/s QPSK transmitter with on-chip T/R switch and fully-differential PLL frequency synthesizer in 65nm CMOS is presented. Direct QPSK modulation is implemented during the first up-conversion, followed by the final up-conversion mixer and power amplifier (PA) as well as on-chip T/R switch. Distributed amplifier technique is utilized to extend the bandwidth of PA. Along with other bandwidth extension techniques, in-band gain variation in signal link is minimized to improve the error vector magnitude (EVM). To reject common-mode noise and improve phase noise performance, a 40GHz fully-differential PLL frequency synthesizer is implemented to provide LO signals and various clocks. The measured output power is 6.4dBm at 60GHz, with 1.2dB gain variation over >6GHz bandwidth. On-chip 27-1 PRBS generators are used to measure the transmitter performance, and the measured EVM is -21.9dB with 5Gb/s QPSK modulation. The transmitter and the PLL & LO distribution network consume 73mW and 62mW, respectively.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"An integrated 60GHz 5Gb/s QPSK transmitter with on-chip T/R switch and fully-differential PLL frequency synthesizer in 65nm CMOS\",\"authors\":\"Lixue Kuang, B. Chi, Lei Chen, Meng Wei, Xiaobao Yu, Zhihua Wang\",\"doi\":\"10.1109/ASSCC.2013.6691070\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An integrated 60GHz 5Gb/s QPSK transmitter with on-chip T/R switch and fully-differential PLL frequency synthesizer in 65nm CMOS is presented. Direct QPSK modulation is implemented during the first up-conversion, followed by the final up-conversion mixer and power amplifier (PA) as well as on-chip T/R switch. Distributed amplifier technique is utilized to extend the bandwidth of PA. Along with other bandwidth extension techniques, in-band gain variation in signal link is minimized to improve the error vector magnitude (EVM). To reject common-mode noise and improve phase noise performance, a 40GHz fully-differential PLL frequency synthesizer is implemented to provide LO signals and various clocks. The measured output power is 6.4dBm at 60GHz, with 1.2dB gain variation over >6GHz bandwidth. On-chip 27-1 PRBS generators are used to measure the transmitter performance, and the measured EVM is -21.9dB with 5Gb/s QPSK modulation. The transmitter and the PLL & LO distribution network consume 73mW and 62mW, respectively.\",\"PeriodicalId\":296544,\"journal\":{\"name\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"209 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2013.6691070\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6691070","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An integrated 60GHz 5Gb/s QPSK transmitter with on-chip T/R switch and fully-differential PLL frequency synthesizer in 65nm CMOS
An integrated 60GHz 5Gb/s QPSK transmitter with on-chip T/R switch and fully-differential PLL frequency synthesizer in 65nm CMOS is presented. Direct QPSK modulation is implemented during the first up-conversion, followed by the final up-conversion mixer and power amplifier (PA) as well as on-chip T/R switch. Distributed amplifier technique is utilized to extend the bandwidth of PA. Along with other bandwidth extension techniques, in-band gain variation in signal link is minimized to improve the error vector magnitude (EVM). To reject common-mode noise and improve phase noise performance, a 40GHz fully-differential PLL frequency synthesizer is implemented to provide LO signals and various clocks. The measured output power is 6.4dBm at 60GHz, with 1.2dB gain variation over >6GHz bandwidth. On-chip 27-1 PRBS generators are used to measure the transmitter performance, and the measured EVM is -21.9dB with 5Gb/s QPSK modulation. The transmitter and the PLL & LO distribution network consume 73mW and 62mW, respectively.