{"title":"计算机体系结构的系统级综合框架","authors":"O. Tanir, V. Agarwal, P. Bhatt","doi":"10.1109/IWRSP.1992.243914","DOIUrl":null,"url":null,"abstract":"A framework for system level synthesis is presented, and a suitable language, DSL, for capturing design specifications and generating control graphs amiable to synthesis is proposed. The three stages in the synthesis process-design specification, intermediate representation, and synthesis-are examined in detail. A rough version of the language is used to model a simple system.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A system level synthesis framework for computer architectures\",\"authors\":\"O. Tanir, V. Agarwal, P. Bhatt\",\"doi\":\"10.1109/IWRSP.1992.243914\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A framework for system level synthesis is presented, and a suitable language, DSL, for capturing design specifications and generating control graphs amiable to synthesis is proposed. The three stages in the synthesis process-design specification, intermediate representation, and synthesis-are examined in detail. A rough version of the language is used to model a simple system.<<ETX>>\",\"PeriodicalId\":210681,\"journal\":{\"name\":\"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWRSP.1992.243914\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWRSP.1992.243914","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A system level synthesis framework for computer architectures
A framework for system level synthesis is presented, and a suitable language, DSL, for capturing design specifications and generating control graphs amiable to synthesis is proposed. The three stages in the synthesis process-design specification, intermediate representation, and synthesis-are examined in detail. A rough version of the language is used to model a simple system.<>