用API15C芯片设计特定的收缩阵列

[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI:10.1109/ASAP.1990.145486

P. Frison, E. Gautrin, D. Lavenier, Jean-Luc Scharbarg

{"title":"用API15C芯片设计特定的收缩阵列","authors":"P. Frison, E. Gautrin, D. Lavenier, Jean-Luc Scharbarg","doi":"10.1109/ASAP.1990.145486","DOIUrl":null,"url":null,"abstract":"The API15C processor, a building block for different systolic structures, is designed exclusively for single-instruction-multiple data (SIMD) execution mode. To support this mode, the instruction set includes special control instructions. Three parallel I/O ports are available for different interconnection schemes. The API15C chip is designed in a CMOS 2- mu m technology. It contains 45000 transistors on a 6-mm $M6.2-mm silicon area. The functionality of the circuit was tested successfully after the first run. It executes one instruction per clock phase of 100 ns, giving a global rate of 10 MIPS. To validate this processing element as a building block for systolic structures, a programmable interface and two single board machines were developed. The first is an 18 processor linear structure able to support a wide range of applications. The second is a 28 processor bidimensional structure for a specific application of string comparison. The instruction set is particularly well-suited for SIMD operation.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"158 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Designing specific systolic arrays with the API15C chip\",\"authors\":\"P. Frison, E. Gautrin, D. Lavenier, Jean-Luc Scharbarg\",\"doi\":\"10.1109/ASAP.1990.145486\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The API15C processor, a building block for different systolic structures, is designed exclusively for single-instruction-multiple data (SIMD) execution mode. To support this mode, the instruction set includes special control instructions. Three parallel I/O ports are available for different interconnection schemes. The API15C chip is designed in a CMOS 2- mu m technology. It contains 45000 transistors on a 6-mm $M6.2-mm silicon area. The functionality of the circuit was tested successfully after the first run. It executes one instruction per clock phase of 100 ns, giving a global rate of 10 MIPS. To validate this processing element as a building block for systolic structures, a programmable interface and two single board machines were developed. The first is an 18 processor linear structure able to support a wide range of applications. The second is a 28 processor bidimensional structure for a specific application of string comparison. The instruction set is particularly well-suited for SIMD operation.<<ETX>>\",\"PeriodicalId\":438078,\"journal\":{\"name\":\"[1990] Proceedings of the International Conference on Application Specific Array Processors\",\"volume\":\"158 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1990] Proceedings of the International Conference on Application Specific Array Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASAP.1990.145486\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990] Proceedings of the International Conference on Application Specific Array Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASAP.1990.145486","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

API15C处理器是不同收缩结构的构建块，专为单指令多数据(SIMD)执行模式而设计。为了支持这种模式，指令集包含了特殊的控制指令。3个并行I/O口可用于不同的互联方案。API15C芯片采用CMOS 2 μ m技术设计。它包含45000个晶体管在一个6毫米$ m6.2毫米硅区域。第一次运行后，电路的功能测试成功。它每100 ns的时钟相位执行一条指令，全局速率为10 MIPS。为了验证该处理元件作为收缩结构的构建块，开发了一个可编程接口和两个单板机器。第一个是18个处理器线性结构，能够支持广泛的应用。第二个是一个28处理器的二维结构，用于字符串比较的特定应用。该指令集特别适合SIMD操作。

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Designing specific systolic arrays with the API15C chip

The API15C processor, a building block for different systolic structures, is designed exclusively for single-instruction-multiple data (SIMD) execution mode. To support this mode, the instruction set includes special control instructions. Three parallel I/O ports are available for different interconnection schemes. The API15C chip is designed in a CMOS 2- mu m technology. It contains 45000 transistors on a 6-mm $M6.2-mm silicon area. The functionality of the circuit was tested successfully after the first run. It executes one instruction per clock phase of 100 ns, giving a global rate of 10 MIPS. To validate this processing element as a building block for systolic structures, a programmable interface and two single board machines were developed. The first is an 18 processor linear structure able to support a wide range of applications. The second is a 28 processor bidimensional structure for a specific application of string comparison. The instruction set is particularly well-suited for SIMD operation.<>

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[1990] Proceedings of the International Conference on Application Specific Array Processors

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