基于FPGA的胎儿无创心率监测系统

R. Rasu, P. S. Sundaram, N. Santhiyakumari
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引用次数: 13

摘要

本文的目的是从母体腹部信号中提取胎儿心电图(FECG)信号,这是医生分析胎儿心脏异常的重要信号。采用基于FIR滤波系数的最小均方自适应滤波方法从母体腹部提取胎儿心电图。该FECG用于计算胎儿心跳和信号周期,基于我们的估计。使用该系统可在妊娠20周后进行FECG检测。为了实时测量脑电图,孕妇应该在腹部系上一条宽腰带,腰带上装有几个心电图电极。从电极收集的数据被发送到一个系统,然后借助自适应噪声消除算法进行分析,该算法用于分离信号。这种分离是通过使用Lab VIEW工具基于预定义的值来完成的。利用Xilinx ISE 12.1对FIR滤波器进行了设计和仿真,并在Spartan 3系列FPGA上实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
FPGA based non-invasive heart rate monitoring system for detecting abnormalities in Fetal
The aim of this paper is to extract the Fetal Electrocardiogram (FECG) signal from the mother's abdomen signal which is an important signal to analyze the abnormalities of the fetal heart by a physician. Fetal ECG is extracted from the mother's abdomen by using least-mean-square (LMS) adaptive filter based on the FIR filter coefficients. This FECG is used to calculate the fetal heart beat and the period of the signal based on our estimation. By using this system FECG can be taken after the pregnancy of 20 weeks. To take FECG in real time, maternal woman should wear a wide belt around her abdomen which is fitted with several ECG electrodes. The data collected from the electrodes are sent to a system and then analyzed with the help of adaptive noise canceller algorithm, which is used to separate the signals. This separation is here done based on predefined values by using the Lab VIEW tool. And also the FIR filter has been designed and simulated using Xilinx ISE 12.1 and implemented in Spartan 3 Family FPGA.
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