A High-Level Model of the Read-Write Control System of a SRAM Chip

A high-level model of the read-write system for a synchronous-pipelined static random access memory (SRAM) was designed using Verilog hardware description language (HDL). The system is comprised of the host, the main controller and the SRAM chip, with the main controller further consisted of the signal source generator and the data transceiver controller. Three read-write modes, non-burst (regular), linear burst and interleaved burst, were realized in this model. The model was validated by behavioral simulations, which showed that the SRAM chip can be written and read correctly in all the operation modes. The SRAM read-write procedure is greatly simplified as the requirements for the source control signals are minimized. The stability and reliability of the system is improved by maximizing the timing margins of the data transmissions.