Simulating the delay in logic networks for large, high-speed computers

When designing a computer with TTL logic circuits, the delays of logic paths have been estimated by considering the number of gate delays and adding in load and media factors. Such a simplistic approach is not accurate enough for calculating delays when designing high-performance large systems using high-speed, non-saturating circuits such as HCML (Honeywell’s Current Mode Logic). There are several reasons: • The clock (cycle) time is considerably faster for a high speed machine, hence the calculations must be very accurate in order to meet performance goals. • The loading on the driving gate varies with the number of driven gates, hence affecting the rise time of the line (interconnect) voltage. • The geometry of the interconnect (branch points, connectors, various media impedances) has an effect on signal propagation with high-speed edges. • Media delay is a significant percentage of path delay as ICs become faster.