An Efficient FPGA implementation of Turbo Product Code decoder with single and double error correction

The paper presents FPGA implementation of turbo product code decoder with single and double error correcting BCH constituent codes that is capable of supporting high throughput and still maintains low complexity. The implementation is based on the Chase-Pyndiah algorithm, which exhibits a modular, simple structure with fine parallelism. Complexity reduction and pipelining for throughput and latency has been done through novel optimizations in submodules of TPC decoder. The resulting turbo decoder is implemented on a Xilinx Virtex-6 customized hardware. Performance comparison against third party IP cores is also presented,