{"title":"支持多个QoS类的可扩展分布式仲裁ATM交换机","authors":"E. Oki, N. Yamanaka, M. Nabeshima","doi":"10.1109/ATM.1999.786875","DOIUrl":null,"url":null,"abstract":"This paper proposes a multi-QoS scalable-distributed-arbitration (MSDA) ATM switch that supports both the high-priority class and the low-priority class under the head-of-line-priority discipline. It has a crosspoint buffer and a transit buffer, each consisting of a high-priority buffer and a low-priority buffer. Arbitration is executed between the crosspoint buffer and the transit buffer in a distributed manner. The MSDA switch extends the advantage of our previously proposed single-QoS scalable-distributed-arbitration (SSDA) switch. It is expandable while permitting high output-line speeds due to the distributed arbitration. The SSDA switch has a problem when its delay-time-based cell selection mechanism is applied to the low-priority class due to the limitation of the number of bits for the delay measure in the cell overhead. We solved this problem by introducing a distributed-ring-arbiter-based cell selection mechanism at each crosspoint for the low-priority class. The low-priority transit buffer at each crosspoint has virtual queues in accordance with the upper input ports. Cells for the low-priority class are selected by distributed ring arbitration among the low-priority crosspoint buffer and the virtual queues at the low-priority transit buffer. Simulations confirm that the MSDA switch ensures fairness in terms of delay time for the high-priority class, while it ensures fairness in terms of throughput for the low-priority class.","PeriodicalId":266412,"journal":{"name":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Scalable-distributed-arbitration ATM switch supporting multiple QoS classes\",\"authors\":\"E. Oki, N. Yamanaka, M. Nabeshima\",\"doi\":\"10.1109/ATM.1999.786875\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a multi-QoS scalable-distributed-arbitration (MSDA) ATM switch that supports both the high-priority class and the low-priority class under the head-of-line-priority discipline. It has a crosspoint buffer and a transit buffer, each consisting of a high-priority buffer and a low-priority buffer. Arbitration is executed between the crosspoint buffer and the transit buffer in a distributed manner. The MSDA switch extends the advantage of our previously proposed single-QoS scalable-distributed-arbitration (SSDA) switch. It is expandable while permitting high output-line speeds due to the distributed arbitration. The SSDA switch has a problem when its delay-time-based cell selection mechanism is applied to the low-priority class due to the limitation of the number of bits for the delay measure in the cell overhead. We solved this problem by introducing a distributed-ring-arbiter-based cell selection mechanism at each crosspoint for the low-priority class. The low-priority transit buffer at each crosspoint has virtual queues in accordance with the upper input ports. Cells for the low-priority class are selected by distributed ring arbitration among the low-priority crosspoint buffer and the virtual queues at the low-priority transit buffer. Simulations confirm that the MSDA switch ensures fairness in terms of delay time for the high-priority class, while it ensures fairness in terms of throughput for the low-priority class.\",\"PeriodicalId\":266412,\"journal\":{\"name\":\"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATM.1999.786875\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE ATM Workshop '99 Proceedings (Cat. No. 99TH8462)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATM.1999.786875","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper proposes a multi-QoS scalable-distributed-arbitration (MSDA) ATM switch that supports both the high-priority class and the low-priority class under the head-of-line-priority discipline. It has a crosspoint buffer and a transit buffer, each consisting of a high-priority buffer and a low-priority buffer. Arbitration is executed between the crosspoint buffer and the transit buffer in a distributed manner. The MSDA switch extends the advantage of our previously proposed single-QoS scalable-distributed-arbitration (SSDA) switch. It is expandable while permitting high output-line speeds due to the distributed arbitration. The SSDA switch has a problem when its delay-time-based cell selection mechanism is applied to the low-priority class due to the limitation of the number of bits for the delay measure in the cell overhead. We solved this problem by introducing a distributed-ring-arbiter-based cell selection mechanism at each crosspoint for the low-priority class. The low-priority transit buffer at each crosspoint has virtual queues in accordance with the upper input ports. Cells for the low-priority class are selected by distributed ring arbitration among the low-priority crosspoint buffer and the virtual queues at the low-priority transit buffer. Simulations confirm that the MSDA switch ensures fairness in terms of delay time for the high-priority class, while it ensures fairness in terms of throughput for the low-priority class.