B.J. Park, Y. Hwang, Y. Hwang, J. Lee, K. Lee, K. Jeong, H. Jeong, Y.J. Park, Kinam Kim
{"title":"一种新颖的位线- stofm(无间隔顶平面掩模)技术,用于90纳米及以后的DRAM生成","authors":"B.J. Park, Y. Hwang, Y. Hwang, J. Lee, K. Lee, K. Jeong, H. Jeong, Y.J. Park, Kinam Kim","doi":"10.1109/VLSIT.2002.1015444","DOIUrl":null,"url":null,"abstract":"A novel bit line technology for self-aligned storage node contact has been developed to overcome the issues related with downscaling of COB stack DRAM cells for the 90 nm DRAM technology node and beyond. In this new scheme, both ILD gap fill tolerance and SAC etching selectivity of SiO/sub 2/ to Si/sub 3/N/sub 4/ are significantly enhanced because there is no need to form Si/sub 3/N/sub 4/ spacer around the bit-line and because of the better profile of top mask Si/sub 3/N/sub 4/. Furthermore, compared to the conventional scheme, the novel bit line has the advantages of device performance such as refresh time and speed because the parasitic bit line capacitance is decreased by as much as 25%. The new bit line technology has been developed and verified with a 0.12 /spl mu/m 512 Mb DRAM product. The results obtained from a 0.12 /spl mu/m DRAM technology confirm that this novel bit line scheme is beneficial for the 90 nm technology node and beyond.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A novel bit line-SToFM (Spacerless top-flat mask)-technology for 90 nm DRAM generation and beyond\",\"authors\":\"B.J. Park, Y. Hwang, Y. Hwang, J. Lee, K. Lee, K. Jeong, H. Jeong, Y.J. Park, Kinam Kim\",\"doi\":\"10.1109/VLSIT.2002.1015444\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel bit line technology for self-aligned storage node contact has been developed to overcome the issues related with downscaling of COB stack DRAM cells for the 90 nm DRAM technology node and beyond. In this new scheme, both ILD gap fill tolerance and SAC etching selectivity of SiO/sub 2/ to Si/sub 3/N/sub 4/ are significantly enhanced because there is no need to form Si/sub 3/N/sub 4/ spacer around the bit-line and because of the better profile of top mask Si/sub 3/N/sub 4/. Furthermore, compared to the conventional scheme, the novel bit line has the advantages of device performance such as refresh time and speed because the parasitic bit line capacitance is decreased by as much as 25%. The new bit line technology has been developed and verified with a 0.12 /spl mu/m 512 Mb DRAM product. The results obtained from a 0.12 /spl mu/m DRAM technology confirm that this novel bit line scheme is beneficial for the 90 nm technology node and beyond.\",\"PeriodicalId\":103040,\"journal\":{\"name\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2002.1015444\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015444","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel bit line-SToFM (Spacerless top-flat mask)-technology for 90 nm DRAM generation and beyond
A novel bit line technology for self-aligned storage node contact has been developed to overcome the issues related with downscaling of COB stack DRAM cells for the 90 nm DRAM technology node and beyond. In this new scheme, both ILD gap fill tolerance and SAC etching selectivity of SiO/sub 2/ to Si/sub 3/N/sub 4/ are significantly enhanced because there is no need to form Si/sub 3/N/sub 4/ spacer around the bit-line and because of the better profile of top mask Si/sub 3/N/sub 4/. Furthermore, compared to the conventional scheme, the novel bit line has the advantages of device performance such as refresh time and speed because the parasitic bit line capacitance is decreased by as much as 25%. The new bit line technology has been developed and verified with a 0.12 /spl mu/m 512 Mb DRAM product. The results obtained from a 0.12 /spl mu/m DRAM technology confirm that this novel bit line scheme is beneficial for the 90 nm technology node and beyond.