Power Optimization of VLSI Scan under Test using X-Filling Technique

Advancements in Very Large-Scale Integrated Technology (VLSI) today has made use of Very Deep Sub-micron (VDSM) technology. This in turn, results in rapid increase in transistor density and proliferation of portable, battery-operated, compact and high-performance smart computing devices. These factors make power minimization a critical defining metric for both design & test engineers. Testing such ICs ought to consider hierarchy levels at various stages of planning a Power-Aware test (including DFT & ATPG) and while developing infrastructure for low-power EDA tools. Over past decade, power management and optimization have become de-facto along with test problem growing by few manifolds as feature size goes down to 10nm [3]. So this paper brings the heuristic approaches of reducing scan power using X-filling in comparison with industrial performance test bound techniques using ISCAS’89 Benchmarking circuits. 70% power reduction is possible using proposed X-filling technique. With novel technique, power reduction upto 63.62% on average basis on shift component and 69.9% on capture component is possible with X-factor reduced upto 0.57 compared to normal scan operation.