铜触点对CMOS前端良率和可靠性的影响

2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI:10.1109/IEDM.2006.346967

G. Van den bosch, S. Demuynck, Z. Tokei, G. Beyer, M. Van Hove, G. Groeseneken

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引用次数: 8

摘要

采用铜触点技术，CMOS前端良率和可靠性取决于触点阻挡层的质量。不良的屏障质量会导致结和栅极介质的良率损失，并减少具有特征击穿特征的击穿时间。故障分析揭示了硅化铜的存在是潜在的原因，其影响取决于受影响区域的确切位置。通过优化屏障，没有迹象表明铜相关的前端良率和可靠性问题

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Impact of copper contacts on CMOS front-end yield and reliability

With copper contact technology, CMOS front-end yield and reliability are governed by the quality of the contact barrier stack. Poor barrier quality gives rise to yield loss in junctions and gate dielectrics, and reduced time-to-breakdown with characteristic breakdown signature. Failure analysis reveals the presence of copper silicide as the underlying cause, its impact depending on the exact location of the affected region. With optimized barrier there is no indication for copper related front-end yield and reliability problems

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来源期刊

2006 International Electron Devices Meeting

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