二维自洽模拟研究三维电荷捕获NAND闪存的保留行为

2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Pub Date : 2014-09-01 DOI:10.1109/SISPAD.2014.6931583

Z. Lun, Shuhuan Liu, Y. He, Yi Hou, K. Zhao, G. Du, Xiaoyan Liu, Yi Wang

{"title":"二维自洽模拟研究三维电荷捕获NAND闪存的保留行为","authors":"Z. Lun, Shuhuan Liu, Y. He, Yi Hou, K. Zhao, G. Du, Xiaoyan Liu, Yi Wang","doi":"10.1109/SISPAD.2014.6931583","DOIUrl":null,"url":null,"abstract":"This paper presents a comprehensive investigation on retention behavior for three-dimensional charge trapping NAND flash memory by two-dimensional self-consistent simulation. Major physical mechanisms, including tunneling, charge trapping and de-trapping process as well as drift-diffusion have been incorporated into the simulator. The developed simulator is able to describe the charge transport along the bitline and in vertical direction in the memory structure. This work aims to help to design and optimize three-dimensional stackable CT-NAND architectures.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"Investigation of retention behavior for 3D charge trapping NAND flash memory by 2D self-consistent simulation\",\"authors\":\"Z. Lun, Shuhuan Liu, Y. He, Yi Hou, K. Zhao, G. Du, Xiaoyan Liu, Yi Wang\",\"doi\":\"10.1109/SISPAD.2014.6931583\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a comprehensive investigation on retention behavior for three-dimensional charge trapping NAND flash memory by two-dimensional self-consistent simulation. Major physical mechanisms, including tunneling, charge trapping and de-trapping process as well as drift-diffusion have been incorporated into the simulator. The developed simulator is able to describe the charge transport along the bitline and in vertical direction in the memory structure. This work aims to help to design and optimize three-dimensional stackable CT-NAND architectures.\",\"PeriodicalId\":101858,\"journal\":{\"name\":\"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"volume\":\"89 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.2014.6931583\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2014.6931583","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 17

摘要

本文采用二维自洽模拟的方法对三维电荷捕获NAND闪存的保留行为进行了全面的研究。主要的物理机制，包括隧道，电荷捕获和释放捕获过程以及漂移扩散已纳入模拟器。所开发的模拟器能够描述存储器结构中沿位线和垂直方向的电荷输运。这项工作旨在帮助设计和优化三维可堆叠CT-NAND架构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Investigation of retention behavior for 3D charge trapping NAND flash memory by 2D self-consistent simulation

This paper presents a comprehensive investigation on retention behavior for three-dimensional charge trapping NAND flash memory by two-dimensional self-consistent simulation. Major physical mechanisms, including tunneling, charge trapping and de-trapping process as well as drift-diffusion have been incorporated into the simulator. The developed simulator is able to describe the charge transport along the bitline and in vertical direction in the memory structure. This work aims to help to design and optimize three-dimensional stackable CT-NAND architectures.

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来源期刊

2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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