{"title":"一种低成本多标准近最优软输出球体解码器:算法与架构","authors":"Özgün Paker, Sebastian Eckert, A. Bury","doi":"10.1109/DATE.2010.5457032","DOIUrl":null,"url":null,"abstract":"We present an algorithm and architecture of a soft-output sphere decoder with an optimized hardware implementation for 2×2 MIMO-OFDM reception. We introduce a novel table look-up approach for symbol enumeration that simplifies the implementation of soft-output decoders. The HW implementation is targeted towards WLAN (IEEE 802.11n) with stringent latency and throughput requirements. The current implementation supports all modulation schemes (BPSK,QPSK,16-QAM, 64-QAM) and shows near-optimal real-time performance. To achieve this, the sphere decoder computes in the worst-case Euclidean distances of 4.1 Giga QAM symbols per second. This challenging requirement is met by a scalable, multi-standard HW architecture which can be tuned to other applications such as LTE, WiMax with no re-design effort. The current instance for WLAN occupies an area of only 0.17 mm2 in 45 nm CMOS technology while providing a guaranteed throughput of 374 Msoftbits/s at 312 MHz clock rate (i.e. outputting 2×6 softbits worst-case every 10 clock cycles).","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"488 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A low cost multi-standard near-optimal soft-output sphere decoder: Algorithm and architecture\",\"authors\":\"Özgün Paker, Sebastian Eckert, A. Bury\",\"doi\":\"10.1109/DATE.2010.5457032\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present an algorithm and architecture of a soft-output sphere decoder with an optimized hardware implementation for 2×2 MIMO-OFDM reception. We introduce a novel table look-up approach for symbol enumeration that simplifies the implementation of soft-output decoders. The HW implementation is targeted towards WLAN (IEEE 802.11n) with stringent latency and throughput requirements. The current implementation supports all modulation schemes (BPSK,QPSK,16-QAM, 64-QAM) and shows near-optimal real-time performance. To achieve this, the sphere decoder computes in the worst-case Euclidean distances of 4.1 Giga QAM symbols per second. This challenging requirement is met by a scalable, multi-standard HW architecture which can be tuned to other applications such as LTE, WiMax with no re-design effort. The current instance for WLAN occupies an area of only 0.17 mm2 in 45 nm CMOS technology while providing a guaranteed throughput of 374 Msoftbits/s at 312 MHz clock rate (i.e. outputting 2×6 softbits worst-case every 10 clock cycles).\",\"PeriodicalId\":432902,\"journal\":{\"name\":\"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)\",\"volume\":\"488 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DATE.2010.5457032\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DATE.2010.5457032","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low cost multi-standard near-optimal soft-output sphere decoder: Algorithm and architecture
We present an algorithm and architecture of a soft-output sphere decoder with an optimized hardware implementation for 2×2 MIMO-OFDM reception. We introduce a novel table look-up approach for symbol enumeration that simplifies the implementation of soft-output decoders. The HW implementation is targeted towards WLAN (IEEE 802.11n) with stringent latency and throughput requirements. The current implementation supports all modulation schemes (BPSK,QPSK,16-QAM, 64-QAM) and shows near-optimal real-time performance. To achieve this, the sphere decoder computes in the worst-case Euclidean distances of 4.1 Giga QAM symbols per second. This challenging requirement is met by a scalable, multi-standard HW architecture which can be tuned to other applications such as LTE, WiMax with no re-design effort. The current instance for WLAN occupies an area of only 0.17 mm2 in 45 nm CMOS technology while providing a guaranteed throughput of 374 Msoftbits/s at 312 MHz clock rate (i.e. outputting 2×6 softbits worst-case every 10 clock cycles).