An Enhanced Simulation Framework for the Performance Evaluation of On-Chip Network Designs

Network-on-Chip (NoC) has emerged as an innovative solution to the communication bottlenecks of the System-on-Chip (SoC) designs. Being an emerging technology, this field requires an extensive research to cope up with the design challenges of the on-Chip networks. In this research work, we have developed and proposed a unified simulation framework named as ENoCTweak for the simulation and analysis of the important parameters such as latency, throughput. energy and power of the NoC system. This framework is mainly an enhanced and updated version of a well-known simulator NoCTweak with additional performance parameters and integration of different NoC components and simulation platforms. Important components from NOCMAP and ReliableNoC simulators are also integrated into the framework of the proposed ENoCTweak simulator. In this platform, we have embedded different mapping algorithms, like Branch & Bound (BB), Simulated Annealing (SA), Segmented Brute-Force Mapping (SBMAP), Branch & Bound based Exact Mapping (BEMAP), and Optimized Near-optimal Mapping (ONMAP) algorithms, in addition to the existing NMAP and Random algorithms. An External Mapping (EXMAP) setup is also developed to evaluate the mapping results of the existing NoC simulation platforms. In addition to the 2D mesh, other topologies like torus and folded torus are implanted to improve the simulation capabilities of the ENoCTweak simulator. Bit energy model along with the CMOS energy models are added to the simulation framework to enhance the characteristic performance of the simulator.