A novel design procedure for tunable low noise amplifiers

A novel design methodology for tunable low noise amplifiers with the associated circuit topology will be presented. The procedure steps based on low noise design essentials are given as the main results of their mathematical analysis using the circuit and noise theory. After the methodology is demonstrated at narrowband by the simulation graphs, the tunability aspect of the design using the series matching at the input and output will be verified. If a tunable capacitor is inserted to the base of the heterojunction bipolar transistor (HBT) at the input, simulation outcomes reveal that for the range of 3.5– 6.5 GHz, input and output return ratios (S11 and S22) can be ensured to be below –10 dB and the difference between noise figure (NF) and minimum noise figure (NFMIN) to be below 0.5 dB.