A Resource Consumption and Performance Overhead Optimized Reduction Circuit on FPGAs

Many scientific and engineering applications involve massive vector operations (such as dot product and matrix multiplication) which can be calculated efficiently by using reduction circuit. However, the low performance and large resource consumption of the reduction circuit limit the ability of the system. In this paper, an optimized reduction circuit with high performance and low resource consumption is proposed, which can handle multiple sets of arbitrary size without pipeline stalling. A new reduction scheduling algorithm is proposed, which consumes fewer cycles and buffer size compared with other methods. Moreover, in order to achieve a high clock frequency, the reduction circuit implements novel status and buffer management modules. The proposed design using a deeply pipelined double-precision floating-point adder as reduction operator is implemented on FPGAs, which achieves at least 1.59 times improvement on area-time product compared with the reported methods.