Design Space Exploration for Heterogenous SoC Integrated with Matrix Accelerator

Accelerators have been widely used in SoC systems as an effective method to improve computing power. There are many ways of which CPU is coupled with accelerator. In this paper, we design a matrix-matrix multiplication accelerator and couple the accelerator with RISC-V CPU in two different forms - independent accelerator and instruction accelerators. Then we evaluate the performance of independent accelerator and new instruction accelerator. The matrix independent accelerator achieves up to 19.6x speedup to the Rocket CPU. And the matrix instruction accelerator achieves up to 44.5x speedup to the Rocket CPU. The instruction accelerator is 2.26x faster than independent accelerator.