{"title":"突发模式存储器改进缓存设计","authors":"Z. Amitai, D. Wyland","doi":"10.1109/ELECTR.1991.718653","DOIUrl":null,"url":null,"abstract":"Burst mode memories improve cache design by improving refill time on cache misses. Burst mode RAMs allow refill of a four word cache line in five clock cycles at 50 mHz rather than the eight clock cycles that would be required for a conventional SRAM. Burst mode RAMs also have clock synchronous interfaces which make them easier to design into systems, particularly at clock rates of 25 mHz and above.","PeriodicalId":339281,"journal":{"name":"Electro International, 1991","volume":"133 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Burst Mode Memories Improve Cache Design\",\"authors\":\"Z. Amitai, D. Wyland\",\"doi\":\"10.1109/ELECTR.1991.718653\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Burst mode memories improve cache design by improving refill time on cache misses. Burst mode RAMs allow refill of a four word cache line in five clock cycles at 50 mHz rather than the eight clock cycles that would be required for a conventional SRAM. Burst mode RAMs also have clock synchronous interfaces which make them easier to design into systems, particularly at clock rates of 25 mHz and above.\",\"PeriodicalId\":339281,\"journal\":{\"name\":\"Electro International, 1991\",\"volume\":\"133 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-04-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electro International, 1991\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ELECTR.1991.718653\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electro International, 1991","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELECTR.1991.718653","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Burst mode memories improve cache design by improving refill time on cache misses. Burst mode RAMs allow refill of a four word cache line in five clock cycles at 50 mHz rather than the eight clock cycles that would be required for a conventional SRAM. Burst mode RAMs also have clock synchronous interfaces which make them easier to design into systems, particularly at clock rates of 25 mHz and above.
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