容错加法器结构的复杂性

2008 Third International Conference on Dependability of Computer Systems DepCoS-RELCOMEX Pub Date : 2008-06-26 DOI:10.1109/DepCoS-RELCOMEX.2008.60

J. Biernat

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引用次数: 3

摘要

为了实现算术电路的容错特性，有几种可能的方法，这些方法在硬件冗余水平和可检测故障的覆盖范围上有所不同。其中只有两种方法适用于快速容错加法器的设计。他们利用了剩余码或双轨码的概念。对不同的快速容错加法器的复杂度进行了比较。

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The Complexity of Fault-Tolerant Adder Structures

To achieve fault-tolerance property of arithmetic circuits several approaches are possible, that differ in the level of hardware redundancy and the coverage of detectable faults. Among them only two are applicable to design of fast fault-tolerant adders. They exploit the concept of residue code or double-rail code. The complexity comparison of the respective fast fault-tolerant adders will be presented.

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2008 Third International Conference on Dependability of Computer Systems DepCoS-RELCOMEX

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