{"title":"采用联合变换相关器的多处理器设计","authors":"M. Alam","doi":"10.1109/NAECON.1993.290794","DOIUrl":null,"url":null,"abstract":"The joint transform correlation technique is used to design a binary multiprocessor that can perform full addition and full subtraction in parallel. A new coding scheme is designed for the proposed technique. Finally, simulation results are presented to verify the effectiveness of the proposed scheme.<<ETX>>","PeriodicalId":183796,"journal":{"name":"Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Multiprocessor design using joint transform correlator\",\"authors\":\"M. Alam\",\"doi\":\"10.1109/NAECON.1993.290794\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The joint transform correlation technique is used to design a binary multiprocessor that can perform full addition and full subtraction in parallel. A new coding scheme is designed for the proposed technique. Finally, simulation results are presented to verify the effectiveness of the proposed scheme.<<ETX>>\",\"PeriodicalId\":183796,\"journal\":{\"name\":\"Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NAECON.1993.290794\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON.1993.290794","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multiprocessor design using joint transform correlator
The joint transform correlation technique is used to design a binary multiprocessor that can perform full addition and full subtraction in parallel. A new coding scheme is designed for the proposed technique. Finally, simulation results are presented to verify the effectiveness of the proposed scheme.<>