Circuit implementation of high-speed pipeline systems

The implementation of high-speed pipeline systems as described in this paper arose as a direct consequence of a large scale Department of Defense developmental effort initiated in 1962. The objective of the effort was to develop and make available a complete capability for producing individual special-purpose systems on a fast reaction basis. From 1962 to the present time attention was focused on all aspects of circuit and packaging technology, automated or computerized design aids, feasibility vehicling, systems design studies, and advanced memory development. As a result of strong industry impetus in these directions it now appears that 1 to 2 nanosecond hybrid integrated or full integrated logic circuits, practical fabrication of transmission line interconnections, packaging densities of 5000 logic gates per cubic foot in the machine environment, 100 to 150 nanosecond cycle time DRO thin film main memories, and 23 to 40 nanosecond integrated scratchpad memories will be made available for systems being constructed over the next one to three year period.