mpeg-4的运动估计体系结构。第9部分:参考硬件描述

International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04. Pub Date : 2004-09-05 DOI:10.1109/ICEEC.2004.1374480

M. Sayed, T. Mohamed, Wael Badawy

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引用次数: 2

摘要

本文介绍了卡尔加里大学在开发BO/IEC JTCl/SC29/WG Il/N5370作为MPEG-4第9部分:参考硬件描述方面的部分贡献。该项目的主要目标是为MPEG-4应用设计一个片上系统平台。设计的模块将在Annapolis Wildcard II上实现。本文提出了一种新的运动估计结构。该模块取代MPEG-4编码器中的运动估计软件模块，辅助MPEG-4软件实现所需的实时约束。所提出的架构使用93 MHz时钟频率在8.712 ms内处理一个CIF视频名称。因此，它可以处理高达114 CIF视频帧每秒。硬件集成，多媒体，MPEG-4。运动估计。

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Motion estimation architecture for mpeg-4 part 9: reference hardware description

This paper presents part of University of Calgary contribution in developing BO/IEC JTCl/SC29/WG Il/N5370 as part of the MPEG-4 Part 9: Reference Hardware Description. The main objective of that project is to design a System-on-Chip platform for MPEG-4 applications. The designed modules will be implemented on Annapolis Wildcard II. New motion estimation architecture is presented in this paper. This module replaces the motion estimation software module in the MPEG-4 encoder to assist the MPEG-4 software to achieve the required real-time constrains. The proposed architecture processes one CIF video pame in 8.712 ms using 93 MHz clock frequency. Therefore, it can process up to 114 CIF video frames per second. Index Terms Hardwarehoftware integration, Multimedia, MPEG-4. Motion Estimation.

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International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.

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