Modeling whispering gallery mode III–V micro-lasers monolithically integrated on Silicon

The vision to speed up on-chip data communication by signal multiplexing using light and the promise to reduce the energy consumption of interconnects using optoelectronic devices has boosted on-chip photonics during the past years. Silicon is an ideal material for optical waveguides and passives, but due to the indirect band gap it is an inefficient emitter. Promising techniques to integrate III-V optoelectronic devices on Si were recently reported using selective area growth in trenches [1], in pre-patterned V-grooves [2], and using template assisted selective epitaxy (TASE) [3] all of which yield optically pumped micro-lasers. Geometric scaling of the photonic devices improves power efficiency due to reduced RC constant, but it is challenging to contact the scaled-down photonic devices. In this work, we employ coupled optoelectronic simulations to evaluate different paths for electrical pumping of our own optically pumped microlasers [3] while considering the constraints given by our process.