Vlsi implementation of nonlinear variable cutoff high pass filter algorithm

The focus of this paper is the actual implementation of the algorithm onto FPGA hardware. A simple nonlinear median based high pass filter algorithm has been implemented using Xilinx ISE 12.2 targeted for FPGA — xc6slx4–3tqg144. The filter structure consists of a median filter followed by a high pass filter. The signal to be filtered is the input to median filter and its output becomes the input to high pass filter. The high pass filter algorithm identifies and separates the high frequency components by sliding a time ordered window of size-3 over the median filter's output samples. This high pass filter preserves the details of filtered low frequency components for reconstruction and not lost as in the case of conventional high pass filter. The hardware performance is studied using Spartan 6.