SPICE Modelling of CNTFET based Neuron Architecture for Low Power and High Speed applications

Very Large-Scale Integration (VLSI) rapidly grew when the Transistor-Transistor Logic (TTL) has much higher power consumption than the Metal-Oxide Semiconductor (MOS) family. The development in the field of electronics have been tremendous since the advent of VLSI. Due to the disadvantages like tunnelling, scaling in Metal Oxide Semiconductor Field Effect Transistors, Carbon nanotubes can be considered as the promising candidate for future devices. Carbon nanotubes are considered as the next generation Field Effect Transistors that can sustain the scalability while increasing its performance. The artificial neural networks are depicted as a structure of interconnected neurons that can figure out values from inputs and are capable of pattern recognition as well as machine learning. The prime aim of this paper is to assimilate techniques that reduce the architecture size using CNTFET technology and decrease the power consumption which leads to higher efficiency and augmented performance of the device. To satisfy the pre-requisites the circuit is designed using 32nm CNTFET technology. The proposed neuron architecture concentrates on the modification of flip flop by replacing the transmission gates with pass transistor by restructuring and reorganisation method to achieve significant delay, power and power delay product utilization. Circuit level simulation for D Flip Flop and neuron Architecture has been performed. The simulation results show that the performance of neuron architecture is improved power by 24.02% with the use of CNTFET, which means the stability is vital than that of MOSFET.