k值数字结构在模拟电路基础上的线性逻辑综合

Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014) Pub Date : 2014-09-01 DOI:10.1109/EWDTS.2014.7027070

N. Prokopenko, N. I. Chernov, V. Yugai

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引用次数: 6

摘要

研究了计算机工程中k值元素逻辑综合的非经典(线性)方法。介绍了不同于传统电路基构建的方法和基本原理。提出了k值逻辑门的新电路方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The linear logic synthesis of k-valued digital structures in the analogous circuitry basis

The non-classical (linear) approach to the logic synthesis of k-valued elements of computer engineering is considered. The method and fundamental principles of building of the circuitry basis, different from traditional ones, are described. The new circuit solutions of k-valued logical gates are suggested.

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Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)

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