低功耗应用的全耗尽CMOS/SOI器件设计指南

Proceedings of 1997 International Symposium on Low Power Electronics and Design Pub Date : 1997-08-01 DOI:10.1145/263272.263361

S. Banna, Philip C. H. Chan, M. Chan, S. Fung, P. Ko

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引用次数: 6

摘要

在本文中，我们报告了低功耗应用的全耗尽CMOS/SOI器件设计指南。讨论了优化工艺、器件和电路参数，并与基于CMOS的批量设计进行了比较。总结了二者的异同。我们相信这是第一次报道这样的研究。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Fully depleted CMOS/SOI device design guidelines for low power applications

In this paper we report the fully depleted CMOS/SOI device design guidelines for low power application. Optimal technology, device and circuit parameters are discussed and compared with bulk CMOS based design. The differences and similarities are summarized. We believe this is the first such study to be reported.

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Proceedings of 1997 International Symposium on Low Power Electronics and Design

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