A Depth-Five Lower Bound for Iterated Matrix Multiplication

We prove that certain instances of the iterated matrix multiplication (IMM) family of polynomials with N variables and degree n require [EQUATION] gates when expressed as a homogeneous depth-five ΣΠΣΠΣ arithmetic circuit with the bottom fan-in bounded by N1/2-e. By a depth-reduction result of Tavenas, this size lower bound is optimal and can be achieved by the weaker class of homogeneous depth-four ΣΠΣΠ circuits.Our result extends a recent result of Kumar and Saraf, who gave the same [EQUATION] lower bound for homogeneous depth-four ΣΠΣΠ circuits computing IMM. It is analogous to a recent result of Kayal and Saha, who gave the same lower bound for homogeneous ΣΠΣΠΣ circuits (over characteristic zero) with bottom fan-in at most N1-e, for the harder problem of computing certain polynomials defined by Nisan--Wigderson designs.