José Velázquez López, J. Ochoa, Daniel Espinobarro, J. Sanchez
{"title":"带有编码误差的LMS算法在DSP TMS320C6713中的分析与实现","authors":"José Velázquez López, J. Ochoa, Daniel Espinobarro, J. Sanchez","doi":"10.1109/CONIELECOMP.2008.7","DOIUrl":null,"url":null,"abstract":"In this work we present the analysis and implementation in a digital signal processor (DSP), of a variant of the least mean square (LMS) algorithm. Modification is based on codifying the error of the algorithm, in order to reduce the design complexity for its implementation in digital adaptive filters, because the error is made up of whole values. The results demonstrate an increase in the convergence speed; it's affected indirectly by the convergence factor, and to obtain a floating point operation reduction, which accelerates processing. These, to demonstrate the results obtained from the implementation of the algorithm in the digital signal processor TMS320C6713 by Texas instruments.","PeriodicalId":202730,"journal":{"name":"18th International Conference on Electronics, Communications and Computers (conielecomp 2008)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Analysis and Implementation of LMS Algorithm with Coding Error in the DSP TMS320C6713\",\"authors\":\"José Velázquez López, J. Ochoa, Daniel Espinobarro, J. Sanchez\",\"doi\":\"10.1109/CONIELECOMP.2008.7\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work we present the analysis and implementation in a digital signal processor (DSP), of a variant of the least mean square (LMS) algorithm. Modification is based on codifying the error of the algorithm, in order to reduce the design complexity for its implementation in digital adaptive filters, because the error is made up of whole values. The results demonstrate an increase in the convergence speed; it's affected indirectly by the convergence factor, and to obtain a floating point operation reduction, which accelerates processing. These, to demonstrate the results obtained from the implementation of the algorithm in the digital signal processor TMS320C6713 by Texas instruments.\",\"PeriodicalId\":202730,\"journal\":{\"name\":\"18th International Conference on Electronics, Communications and Computers (conielecomp 2008)\",\"volume\":\"71 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-03-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"18th International Conference on Electronics, Communications and Computers (conielecomp 2008)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CONIELECOMP.2008.7\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"18th International Conference on Electronics, Communications and Computers (conielecomp 2008)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CONIELECOMP.2008.7","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis and Implementation of LMS Algorithm with Coding Error in the DSP TMS320C6713
In this work we present the analysis and implementation in a digital signal processor (DSP), of a variant of the least mean square (LMS) algorithm. Modification is based on codifying the error of the algorithm, in order to reduce the design complexity for its implementation in digital adaptive filters, because the error is made up of whole values. The results demonstrate an increase in the convergence speed; it's affected indirectly by the convergence factor, and to obtain a floating point operation reduction, which accelerates processing. These, to demonstrate the results obtained from the implementation of the algorithm in the digital signal processor TMS320C6713 by Texas instruments.