伪随机数生成的全数字混沌振荡器的短期可预测性

A. Radwan, A. S. Mansingka, Mohammed Affan Zidan, K. Salama
{"title":"伪随机数生成的全数字混沌振荡器的短期可预测性","authors":"A. Radwan, A. S. Mansingka, Mohammed Affan Zidan, K. Salama","doi":"10.1109/ICECS.2013.6815432","DOIUrl":null,"url":null,"abstract":"This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation. Short-term predictability is studied in relation to system precision, Euler step size and attractor size and optimal parameters for maximum performance are derived. Defective bits from the native chaotic output are neglected and the remaining pass the NIST SP. 800-22 tests without post-processing. The resulting optimized pseudorandom number generator has throughput up to 17.60 Gbits/s for a 64-bit design experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.85%.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"On the short-term predictability of fully digital chaotic oscillators for pseudo-random number generation\",\"authors\":\"A. Radwan, A. S. Mansingka, Mohammed Affan Zidan, K. Salama\",\"doi\":\"10.1109/ICECS.2013.6815432\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation. Short-term predictability is studied in relation to system precision, Euler step size and attractor size and optimal parameters for maximum performance are derived. Defective bits from the native chaotic output are neglected and the remaining pass the NIST SP. 800-22 tests without post-processing. The resulting optimized pseudorandom number generator has throughput up to 17.60 Gbits/s for a 64-bit design experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.85%.\",\"PeriodicalId\":117453,\"journal\":{\"name\":\"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2013.6815432\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2013.6815432","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

本文利用欧拉近似给出了一个三阶混沌系统的数字实现。研究了短期可预测性与系统精度的关系,导出了欧拉步长、吸引子大小和性能最大化的最优参数。原生混沌输出中的缺陷位被忽略,剩余的通过NIST SP. 800-22测试,无需后处理。在Xilinx Virtex 4 FPGA上进行了实验验证,得到的64位伪随机数生成器吞吐量高达17.60 Gbits/s,逻辑利用率低于1.85%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
On the short-term predictability of fully digital chaotic oscillators for pseudo-random number generation
This paper presents a digital implementation of a 3rd order chaotic system using the Euler approximation. Short-term predictability is studied in relation to system precision, Euler step size and attractor size and optimal parameters for maximum performance are derived. Defective bits from the native chaotic output are neglected and the remaining pass the NIST SP. 800-22 tests without post-processing. The resulting optimized pseudorandom number generator has throughput up to 17.60 Gbits/s for a 64-bit design experimentally verified on a Xilinx Virtex 4 FPGA with logic utilization less than 1.85%.
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