Control-flow guided property directed reachability for imperative synchronous programs

Property directed reachability (PDR) has been introduced as a very efficient verification method for synchronous hardware circuits that is based on induction rather than fixpoint iteration. However, hardware circuits are usually synthesized from more abstract high-level languages like synchronous languages (or synchronous subsets of hardware description languages). In this paper, we show that it is possible to derive from such high-level languages additional control-flow information that can be added to the transition relation to make PDR even more efficient. As will be shown, PDR can benefit from this additional information since many safety properties become inductive only with respect to the enhanced transition relations. The added control-flow information is not needed for the synthesis and is therefore not explicitly encoded in the generated systems, but it can be easily derived from the original programs and used for verification. We present two methods to compute additional control-flow information that differ in how precisely they approximate the reachable control-flow states and also in the runtime required for their computation.