基于CMOS技术的单通道5bit 333MS/s异步数字斜率ADC

2017 3rd International Conference on Computational Intelligence & Communication Technology (CICT) Pub Date : 2017-02-01 DOI:10.1109/CIACT.2017.7977324

Yujun Shu, Fengyi Mei, Youling Yu

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摘要

本课题设计并实现了一个5位333MS/s数字斜率ADC(模数转换器)。在中芯国际55nm CMOS工艺下，利用Cadence工具进行了实现和仿真。电源为1.2 V，采用改进的延迟单元，可将延迟时间缩短至50ps。此外，一个自禁用比较器被用来节省电力。当输入峰峰值为0.4V时，SNDR(信噪比)为28.19 dB, ENOB(有效比特数)为4.39 bit, SFDR(无杂散动态范围)为35.87 dB, SNR(信噪比)为31.47dB。

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A single-channel 5bit 333MS/s asynchronous digital slope ADC based on CMOS technology

This project design and present a 5-bit 333MS/s digital slope ADC (analog-to-digital converter. It is implemented and simulated with Cadence tool in SMIC 55nm CMOS technology. The power supply is 1.2 V and the improved delay cells are used which can shorten the delay time to 50ps. In addition, a self-disabled comparator is used to save power. When the peak-to-peak value of input is 0.4V, the SNDR(Signal to Noise and Distortion Ratio) is 28.19 dB, ENOB(Effective Number of Bits)is 4.39 bit, SFDR(Spurious Free Dynamic Range) is 35.87 dB, SNR(Signal-to-Noise Ratio)is 31.47dB.

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2017 3rd International Conference on Computational Intelligence & Communication Technology (CICT)

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