Symmetrical dense disparity estimation: algorithms and FPGAs implementation

In this paper. we propose new algorithms of window-hased disparip estimation‘hi-level window refinement ’ and ‘Svmmetrical Search ’, and modifi conventional fast algorithm‘Partial Sum Approach ’. With these algorithms. we can achieve 1600MDPS with implementing to FPGA.7 rising 10% oJFPGAs area. and it can generate dense disparip map which has size of marimrim 1024 hv 1024 andframe rate of 47 frame.7 per second. It is 20 times as fast as the disparip estimator used in tliese daw. Our disparip map is smooth in planar area. hut detail in discontinuous area. In this paper. we will show the process for implementation and compare the result with conventional algorithms for hardware. as well as complicate algorithms for sofhmre. We have confirmed the proper qualitative peformance for IVR in processing the experiments in the end’. Index Terms FPGAs, disparity estimation, implementation, stereo.