New Gen Algorithm for Detecting Sag and Swell Voltages in Single Phase Inverter System

In this manuscript, a novel sag and peak detector by means of a delta square operation for a single-phase is suggested. The established sag detector is from a single phase digital phase-locked loop (DPLL) that is founded on a d-q transformation employing an all-pass filter (APF). The d-q transformation is typically employed in the three-phase coordinate system. The APF produces a virtual phase with a 90 deg phase delay, but the virtual phase can not reproduce an abrupt variation of the grid voltage, at the moment in which the voltage sag transpires. As a consequence, the peak value is severely garbled, and settles down gradually. A modified APF produces the virtual q-axis voltage factor from the difference between the current and the former value of the d-axis voltage component in the stationary reference frame.  Nevertheless, the amended APF cannot sense the voltage sag and peak value when the sag transpires around the zero crossing points such as 0 deg and 180 deg since the difference voltage is not adequate to sense the voltage sag. The suggested algorithm is proficient to sense the sag voltage through all regions as well as the zero crossing voltage. Furthermore, the precise voltage drop can be obtained by computing the q-axis component, which is relational to the d-axis component. To authenticate the legitimacy of the suggested scheme, the orthodox and suggested approaches are contrasted by means of the simulations and investigational results.