3D Test Wrapper Chain Optimization with I/O Cells Binding Considered

Previous 3D test wrapper chain synthesis algorithms do not consider the binding of I/O cells (i.e., the association between scan chains and I/O cells). However, the binding of I/O cells may be specified as synthesis constraints. In this paper, we propose a 3D test wrapper chain optimization algorithm with I/O cells binding considered. Our objective is not only to reduce the required test time but also to reduce the number of test TSVs (through-silicon-vias) under I/O cells binding constraints. Our experiments show that the proposed algorithm greatly reduces both test time and test TSV count.