Workflow for multi-core architecture: From MATLAB/Simulink models to hardware mapping/scheduling

Programming multicore based Digital Signal Processors (DSP) becomes increasingly complex. This complexity is related to the rapid evaluation of Telecommunication and multimedia systems accompanied by a rapid increase of user requirements in terms of latency, power computation, consumption, etc. Workflow showed to be a successful approach for programming the applications based on multi-cores DSP platforms. The main goal of this work is the design of a hardware/software system in an automated manner. In this paper, we present our proposed workflow taking as entry point a MATLAB/Simulink application. This workflow allows an automatic transformation from a Simulink model to synchronous dataflow (SDF) model, followed by a mapping and scheduling steps in order to obtain the C code to be executed by each core within the designed platform. Our approach is based on the synchronous and hierarchical behaviour of both Simulink and SDF, aiming to simplify the generation of a compatible C code. We present also a performance analysis to find an optimal number of cores to be used for a configured MIMO OFDM LTE that we give as example.