采用RZ DAC对三阶CT ΔΣ CRFB-FF结构调制器进行过量环路延迟补偿

P.Emi Pushpam, J. Twinkle, Dr.Premanand V.Chandramani
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引用次数: 0

摘要

连续时间δ - σ调制器(CT-DSM)存在系统级非理想性,即过量环路延迟。这种多余的环路延迟改变了NTF(噪声传递函数)并影响调制器的稳定性。如果延迟值在0到0.5之间,则归零DAC (RZ-DAC)解决了这个问题。在量化器周围添加一个额外的路径来补偿0.1到1范围内多余的环路延迟。但这需要事先知道延迟值。本文提出了一种简单的补偿任何未知延迟值大于1的多余环路延迟的技术。补偿技术使用RZ-DAC和一个额外的补偿环路,延迟$\ mathm {z}^{-1/2}$和围绕量化器的简单修改。为了验证补偿技术的有效性,本文选择了具有CRFBFF结构的三阶CT-DSM。调制器实现恒定的S(Q)NR为87。4dB,环路延迟在信号链中高达1。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Excess loop delay compensation using RZ DAC for the third order CT ΔΣ modulator with CRFB-FF structures
Continuous-time Delta-Sigma Modulators (CT-DSM) suffer from one of the system-level non-idealities called an excess loop delay. This excess loop delay changes the NTF (Noise Transfer Function) and affects the stability of the modulator. Return-To-Zero DAC (RZ-DAC) solves this problem if the delay value is ranged between 0 and 0.5. Adding an additional path around the quantizer compensate the excess loop delay for the range 0.1 to 1. But this requires the delay value to be known before. A simple technique for compensating excess loop delay for any unknown delay values up-to 1 is suggested in this paper. The compensation technique uses RZ-DAC with an additional compensation loop with delay $\mathrm{z}^{-1/2}$ and a simple modification around the quantizer. To verify the compensation technique the third order CT-DSM with CRFBFF structure has been chosen. The modulator achieves constant S(Q)NR of 87. 4dB with loop delay up-to 1 in the signal chain.
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