A. Kennedy, J. Simpson, Pankaj Kumar, Ayenda Kemp, K. Awate, K. Manning
{"title":"4.1介绍","authors":"A. Kennedy, J. Simpson, Pankaj Kumar, Ayenda Kemp, K. Awate, K. Manning","doi":"10.14361/9783839452431-015","DOIUrl":null,"url":null,"abstract":"In Chapter 1 we learned how to make chips that work. Now we move on to making chips that work well, where \" well \" can be defined as fast, low in power, inexpensive to manufacture , reliable, etc. Before we can choose which design alternative is best, we must develop ways to estimate the goodness of each option, especially with regard to speed and power consumption. The most obvious way to characterize a circuit is through simulation, and that will be the topic of Chapter 5. Unfortunately, simulations only inform us how a particular circuit behaves, not how to change the circuit to make it better. Moreover, if we don't know approximately what the result of the simulation should be, we are unlikely to catch bugs in our simulation model. Mediocre engineers rely predominantly on computer tools, but outstanding engineers develop their physical intuition to rapidly estimate the behavior of circuits. In this chapter we are primarily concerned with the development of simple models that will assist us in the understanding of system performance. In a modern process, interconnect performance can be as important as or even more important than transistor performance. The issues to be considered in this chapter are Delay estimation in CMOS gates Power dissipation of CMOS logic Interconnect delay and signal integrity Design margining Reliability Effects of scaling","PeriodicalId":263614,"journal":{"name":"Curating Contemporary Music Festivals","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"4.1 Introduction\",\"authors\":\"A. Kennedy, J. Simpson, Pankaj Kumar, Ayenda Kemp, K. Awate, K. Manning\",\"doi\":\"10.14361/9783839452431-015\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In Chapter 1 we learned how to make chips that work. Now we move on to making chips that work well, where \\\" well \\\" can be defined as fast, low in power, inexpensive to manufacture , reliable, etc. Before we can choose which design alternative is best, we must develop ways to estimate the goodness of each option, especially with regard to speed and power consumption. The most obvious way to characterize a circuit is through simulation, and that will be the topic of Chapter 5. Unfortunately, simulations only inform us how a particular circuit behaves, not how to change the circuit to make it better. Moreover, if we don't know approximately what the result of the simulation should be, we are unlikely to catch bugs in our simulation model. Mediocre engineers rely predominantly on computer tools, but outstanding engineers develop their physical intuition to rapidly estimate the behavior of circuits. In this chapter we are primarily concerned with the development of simple models that will assist us in the understanding of system performance. In a modern process, interconnect performance can be as important as or even more important than transistor performance. The issues to be considered in this chapter are Delay estimation in CMOS gates Power dissipation of CMOS logic Interconnect delay and signal integrity Design margining Reliability Effects of scaling\",\"PeriodicalId\":263614,\"journal\":{\"name\":\"Curating Contemporary Music Festivals\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Curating Contemporary Music Festivals\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.14361/9783839452431-015\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Curating Contemporary Music Festivals","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.14361/9783839452431-015","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In Chapter 1 we learned how to make chips that work. Now we move on to making chips that work well, where " well " can be defined as fast, low in power, inexpensive to manufacture , reliable, etc. Before we can choose which design alternative is best, we must develop ways to estimate the goodness of each option, especially with regard to speed and power consumption. The most obvious way to characterize a circuit is through simulation, and that will be the topic of Chapter 5. Unfortunately, simulations only inform us how a particular circuit behaves, not how to change the circuit to make it better. Moreover, if we don't know approximately what the result of the simulation should be, we are unlikely to catch bugs in our simulation model. Mediocre engineers rely predominantly on computer tools, but outstanding engineers develop their physical intuition to rapidly estimate the behavior of circuits. In this chapter we are primarily concerned with the development of simple models that will assist us in the understanding of system performance. In a modern process, interconnect performance can be as important as or even more important than transistor performance. The issues to be considered in this chapter are Delay estimation in CMOS gates Power dissipation of CMOS logic Interconnect delay and signal integrity Design margining Reliability Effects of scaling